1. Field of the Invention
The present invention relates to circuits for transferring data to and from a recording medium and, in particular, to circuits of a magneto-resistive read head.
2. Description of the Related Art
Conventional recording systems of the prior art encode data and write the encoded data to a recording medium, such as a magnetic hard drive or an optical recording disc. A read channel component is an integrated circuit (IC) of a computer hard disk (HD) drive that encodes, detects, and decodes data, enabling a read/write head to correctly i) write data to the disk drive and ii) read back the data. The encoded data is written to the disc (or other recording medium) by a read/write head. In a magnetic recording system, data is recorded by a head by varying the magnetic field over a bit position (“cell”) on the surface of the recording disc. Data is read by sensing magnetic variations corresponding to the data as the head passes over the cell.
Two types of disc drive systems might be employed to write information to or read information from a disc. One type is an inductive write/inductive read system, and the other type is an inductive write/magneto-resistive (MR) read system. Inductive write/inductive read systems employ a single inductive element (coil) that is used to both write and read data. However, as track densities increase, mismatch between ideal coil settings for write and read operations due to resonance frequency changes decreases the data bandwidth. Consequently, for inductive write/MR read systems, an inductive element is selected and optimized for write operations, while an MR element is employed for read operations. The MR element is a resistive element that is biased, either by voltage or current, and variations in the magnetic field detected by the MR element result in variations in the resistance value of the MR element. Variations in resistance of the MR element produce signal variations that are subsequently amplified by a preamplifier and provided as the detected data. An MR read head generally comprises the MR element, while the MR reader generally comprises at least a portion of the preamplifier having MR bias and other control loop circuitry (also termed an MR reader).
The resistance of a particular MR element in a given manufacturer's disk drive can vary over a wide range. It is desirable to accommodate head-to-head MR element resistance variations of 4:1 and higher in a given preamplifier design used in conjunction with the MR element. The value of the MR resistance (RMR) affects the design of a disk drive preamplifier used to amplify signals from the MR element. Head-to-head variations in RMR affect i) the gain and bandwidth of an MR element bias loop used to provide current/voltage bias to the MR element, ii) the setting of a low corner frequency of the MR reader, and iii) read-to-write and write-to-read transition times. Write-to-read transition time and read-to-write transition time are measures of the preamplifier's ability to quickly switch between operating modes.
In write mode, reduced or no bias voltage is applied to the MR element, because edge rates of the writer output are very fast. These edge rates might be fast enough to travel down the writer traces of the flex interconnect from the writer output of the preamplifier to the inductive write head, coupling across the interconnect to the reader traces on the flex interconnect which connect the MR element to the reader input of the preamplifier. Overbiasing the MR element can cause damage to the read head and reduce the read head's life span. So, reducing or removing the bias voltage placed across the MR element and pulling the read head to ground protects the MR element during write mode. When the preamplifier is in write mode, the MR bias loop is in slow mode for two reasons. First, in slow mode, the bandwidth of the loop is low so that any coupling due to the fast edges of the writer signal into the MR bias loop is ignored, and second, operating the MR bias loop in slow mode reduces power consumption. The difference between fast and slow modes is the MR bias feedback loop unity gain frequency. The unity gain frequency determines the rate that the MR bias can change.
When the preamplifier switches from write mode to read mode during the write-to-read transition, a bias voltage is applied relatively quickly to the MR element so that data may be read from the disk without wasting time or disk space. The preamplifier switches into fast mode so that the desired voltage applied to the MR element can be quickly reached. The MR bias loop then switches back into slow mode. In slow mode, the unity gain frequency of the MR bias loop is set below that of the lowest frequency content of the data to be read so that MR bias loop operation does not corrupt the data being read from the disk.
In read mode, the MR element has some bias voltage (or current) applied to it, and data is read from the disk. The MR bias loop operates in slow mode so as not to corrupt the data being read from the disk. As the preamplifier switches from read mode to write mode during the read-to-write transition, the MR bias loop switches into fast mode so that the bias voltage may be either reduced or removed altogether when in write mode. After the desired bias voltage level for write mode is reached, the MR bias loop switches back into slow mode.
Variations in MR resistance change the gain of the MR bias loop, thus affecting the MR bias loop's performance and stability. FIG. 1 shows a block diagram of prior art MR bias loop 100 that biases the MR element RMR in an MR reader. The voltage VMR across RMR (VMR is the voltage between nodes Vmr+ and Vmr−) is sensed and compared to a programmable offset voltage inside of gain stage 110. Gain stage 110 amplifies the difference between VMR and the programmable offset voltage by amplification factor A to provide output voltage VERR. The resulting output voltage VERR of gain stage 110 is amplified by transconductance stage 111 (with transconductance Gm, i.e., the slope of the transconductance stage's operating transfer characteristic).
The output signal of transconductance stage 111 is integrated via capacitor CINT, with the voltage across CINT employed to bias RMR through bias resistors RB1 and RB2 (RB1 substantially equals RB2 equaling RB) via isolating (unity-gain) amplifiers 102 and 103. MR bias loop 100 operates to drive VERR to zero volts (differential). When VERR is zero volts (differential), the bias voltage applied to the MR element RMR is equal to the programmable offset voltage.
The DC loop gain Aloop(DC) of MR bias loop 100 is given in equation (1):
                                          A                          loop              ⁡                              (                DC                )                                              =                                    AGmR              0                        ⁡                          (                                                R                  MR                                                                      R                    MR                                    +                                      2                    ⁢                                          R                      B                                                                                  )                                      ,                            (        1        )            where A is a constant and R0 is the output impedance of transconductance stage 111. The unity gain bandwidth (UGB) of MR bias loop 100 is given in equation (2):
                    UGB        =                                                            AGmR                0                            ⁡                              (                                                      R                    MR                                                                              R                      MR                                        +                                          2                      ⁢                                              R                        B                                                                                            )                                      ⁢                          (                              1                                  2                  ⁢                                                                          ⁢                  π                  ⁢                                                                          ⁢                                      R                    0                                    ⁢                                      C                    INT                                                              )                                =                                    (                                                AGmR                  MR                                                  2                  ⁢                                                                          ⁢                  π                  ⁢                                                                          ⁢                                                            C                      INT                                        ⁡                                          (                                                                        R                          MR                                                +                                                  2                          ⁢                                                      R                            B                                                                                              )                                                                                  )                        .                                              (        2        )            As shown in equation (1), a higher value of RMR yields a larger loop gain Aloop(DC), which may lead to loop instability. As shown in equation (2), a higher value of RMR also causes an increase in UGB.
The setting of a low corner frequency fLC of the MR reader also varies with variations in the MR resistance RMR. A second loop (“low corner frequency (LCF) loop”) controls fLC of the first gain stage of the MR reader. For inductive write/MR read systems, a cross-coupled current sense (CCCS) reader is a preamplifier circuit that is employed with the MR element to read data from a recording medium. FIG. 2 shows CCCS reader 200 employed as the first gain stage of an MR reader. CCCS reader 200 is configured such that the changing magnetic field of the cell causes current variations in the MR element (RMR) as the element moves over the cell. CCCS reader 200 amplifies the current variations through RMR caused by varying differential input voltage VIN(=Vmr) across RMR, and translates them into an output signal VOUT representing sensed data. CCCS reader 200 includes a driver section for the voltage across RMR including transistors M1 and M2, load resistors RL1 and RL2 (RL1 equals RL2 equals RL), and current sources IA1 and IA2 that are configured as a differential amplifier through transconductance stage 201. CCCS reader 200 employs AC coupling of the driver section to transconductance stage 201 (through transistors Q1 and Q2, current sources IA3 and IA4, and coupling capacitors CCC1 and CCC2 (CCC1 equals CCC2 equals CCC).
The low corner frequency fLC of CCCS reader 200 is set to pass the lowest frequency content of the data being read from the disk while rejecting frequency content beneath that of the data. The unity gain bandwidth of the MR bias loop is maintained beneath that of fLC of CCCS reader 200. Otherwise, operation of the MR bias loop interacts with operation of the LCF loop, causing peaking in the frequency response of CCCS reader 200 and possible circuit instability. Furthermore, if the UGB of the MR bias loop extends to the frequency of data being read from the disk, then the MR bias loop corrupts the read data while attempting to maintain a constant bias across the MR read head.
However, it is desirable to maintain as high a gain as is possible in the MR bias loop so as to maximize accuracy of the MR bias loop. Thus, system designs that allow for a large variation in MR resistance make a trade-off between i) MR bias loop accuracy for low values of RMR and ii) UGB for high values of RMR.
The low corner frequency fLC of the MR reader is set by the gain of CCCS reader 200, the transconductance during slow mode (denoted by GmReader) of the CCCS reader 200, and the capacitance of the cross-coupling capacitors in the first gain stage of CCCS reader 200. The low corner frequency fLC is proportional to the approximation given in equation (3):
                                          f            LC                    ∝                                    AGm              Reader                                      C              CC                                ≈                                    2              ⁢                              R                L                            ⁢                              Gm                Reader                                                                    R                MR                            ⁢                              C                CC                                                    ,                            (        3        )            
As shown in equation (3), fLC of CCCS reader 200 decreases as the value of RMR increases, which is the opposite of the effect of increasing RMR on the UGB of the MR bias loop. The risk of overlapping between i) the loop bandwidths of the MR bias loop and ii) the LCF loop setting the fLC, thus interfering with one another, due to variations in RMR increases substantially for larger variation range of RMR.
Read head voltage slew rate also varies with variations in RMR. The read head voltage slew rate is a measure of the preamplifier's (MR reader's) ability to rapidly change the bias voltage across the read head when switching between write and read operations. MR readers are increasingly sensitive to overbias conditions. Placing too large a voltage across the MR element significantly reduces the life expectancy of the head, and so avoiding voltage overshoot while ramping up the voltage across the MR element is desirable. While writing data to the disk, the MR bias circuit that provides the bias to the MR element may be turned off and both ends of the read head pulled to ground to minimize damaging effects from write head signals coupling onto the MR element. However, the MR reader should switch quickly from write mode into read mode to avoid wasting valuable disk space.
Referring to FIG. 1, there is a constant slew rate across integration capacitor CINT. The slew rate S is set by the maximum output current IGmMAX of transconductance stage 111 and the value of CANT and is as given by equation (4):
                    S        =                                            I              GmMAX                                      C              INT                                .                                    (        4        )            
However, the slew rate SHEAD seen at the MR read head (across the MR element) varies proportionally to the value of RMR. The slew rate SHEAD at the MR element is given in equation (5):
                              S          HEAD                =                                            I              GmMAX                                      C              INT                                ⁢                      (                                          R                MR                                                              R                  MR                                +                                  2                  ⁢                                      R                    B                                                                        )                                              (        5        )            
With a range of values for RMR between 15Ω and 70Ω, and a typical value for RB of approximately 300Ω, the variation in slew rate at the MR read head may vary by approximately 4:1.
To minimize preamplifier switching time from write mode to read mode (the write-to-read recovery time), the maximum output current IGmMAX of transconductance stage 111 in MR bias loop 100 of FIG. 1 can be increased during this transition time. Increasing IGmMAx increases the slew rate seen at the MR reader, as given by equation (5). The value of Gm of transconductance stage 111 in MR bias loop 100 can be increased to a higher value during this transition from write mode into read mode. The increased value of Gm increases the UGB of the MR bias loop to maintain stability with the increased slew rate, which might be accomplished by i) increasing a tail current in a transconductance stage (Gm-stage) undegenerated differential pair, or ii) operating two Gm-stages in parallel. For the second method, a low-gain Gm-stage and a high-gain Gm-stage are used. The high-gain Gm stage is active only during the write mode to read mode transition.
With a faster slew rate seen at the MR read head, fLC of the first gain stage (e.g., CCCS reader 200) is also increased so that the LCF loop can track the rapid change in MR bias voltage without i) interfering with the MR bias loop, ii) causing overshoot in the MR bias voltage, or iii) instability. Increasing fLC of the first gain stage might be accomplished in a manner similar to that described for minimizing the preamplifier switching time by increasing the UGB of MR bias loop 100. The slew rate across the cross-coupling capacitors, CCC1 and CCC2, and the gain of the transconductance stage, GmREADER, are set to relatively high values during this write-to-read transition time, while still maintaining loop stability. This slew rate across the cross-coupling capacitors and the gain of the transconductance stage during this write-to-read transition time determine the maximum slew rate allowed at the MR read head. The maximum slew rate seen at the head occurs when RMR is at its maximum value, but to slew from zero volts across the read head to its final value (given the previously described range of values for RMR) might take up to four times longer when RMR is at its minimum value.